Search - vhdl controller

[VHDL-FPGA-Verilog] USB_VHDL_CODE

Description: USB接口控制器参考设计VHDL代码,方便开发FPGA人员进行USB的开发，是一个不错的源码。-USB interface controller reference design VHDL code, facilitate the development of FPGA personnel USB development, is a good source.
Platform: | Size: 60416 | Author: hyl | Hits:

[File Format] designforvideobasedonSDRAM

Description: 在信息处理中，特别是实时视频图像处理中，通常都要对实现视频图像进行处理，而这首先必须设计大容量的存储器，同步动态随机存储器SDRAM虽然有价格低廉、容量大等优点，但因SDRAM的控制结构复杂，常用的方法是设计SDRAM通用控制器，这使得很多人不得不放弃使用SDRAM而使用价格昂贵的SRAM。为此，笔者在研究有关文献的基础上，根据具体情况提出一种独特的方法，实现了对SDRAM的控制，并通过利用FPGA控制数据存取的顺序来实现对数字视频图像的旋转，截取、平移等实时处理。-In information processing, especially real-time video image processing usually have to deal with video images, which must first be designed large-capacity memory, synchronous dynamic random access memory SDRAM Although there are low cost, large capacity, etc., but SDRAM control structure of the complex, commonly used method is to design generic SDRAM controller, which makes a lot of people had to abandon the use of SDRAM and the use of expensive SRAM. To this end, the authors examine the literature based on the specific situation in a unique way to realize the control of SDRAM, and control data through the use of FPGA to realize the order of access to digital video image rotation, interception, translation, such as real-time processing.
Platform: | Size: 137216 | Author: 赵明玺 | Hits:

[VHDL-FPGA-Verilog] bch_encoder_decoder

Description: bch encoder+decoder 源代码，Flash控制器，通讯都需要用到哦-bch encoder+ decoder source code, Flash controller, communications are needed Oh
Platform: | Size: 136192 | Author: linchan | Hits:

[VHDL-FPGA-Verilog] cpu-leon3-altera-ep2s60-ddr

Description: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
Platform: | Size: 752640 | Author: zhao onely | Hits:

[Other Embeded program] electripoweranalyze

Description: 电网参数的测量和检测，如何运用VHDL语言设计采集数据控制器，-Grid parameter measurement and testing, how to use VHDL design language acquisition data controller,
Platform: | Size: 330752 | Author: 葛铃铃 | Hits:

[VHDL-FPGA-Verilog] adc0809

Description: VHDL编写的ADC0809 控制器，经过验证没有错误-VHDL prepared ADC0809 controller, no errors verified
Platform: | Size: 1024 | Author: 王攀 | Hits:

[Other systems] fpga+1602

Description: 本程序用VHDL语言编程实现FPGA对点阵液晶1602的驱动 -This procedure using VHDL language programming FPGA to realize the 1602 dot-matrix LCD driver
Platform: | Size: 1024 | Author: pdu | Hits:

[VHDL-FPGA-Verilog] Intel_Flash

Description: intel flash控制器VHDL 源代码-intel flash controller VHDL source code
Platform: | Size: 19456 | Author: maliang | Hits:

[Software Engineering] USB_devide

Description: 利用最新的嵌入式开发工具EDK，在FPGA 中完成对PDIUSBD12 的硬件定制和固件编程，从而在FPGA 中实现U S B 控制器，并最终完成U S B 的枚举过程、驱动程序的开发和简单的应用。-Using the latest embedded development tools, EDK, in the FPGA completes its PDIUSBD12 custom hardware and firmware programming, in order to realize USB controller in the FPGA, and ultimately complete the USB enumeration process of driver development and simple应用.
Platform: | Size: 50176 | Author: pengrong | Hits:

[VHDL-FPGA-Verilog] ps2_verilog

Description: ps2_键盘控制器源码verilog源码，是一个不错的代码-ps2_ keyboard controller Verilog source code, is a good code
Platform: | Size: 13312 | Author: 高鹏 | Hits:

[Embeded-SCM Develop] EP1C6_12_4_VgaPb

Description: 基于fpga和sopc的用VHDL语言编写的EDA的VGA图像显示控制器-FPGA and SOPC based on the use of VHDL language EDA s VGA graphics display controller
Platform: | Size: 147456 | Author: 多幅撒 | Hits:

[Embeded-SCM Develop] EP1C6_12_12_VGAgame

Description: 基于fpga和sopc的用VHDL语言编写的EDA的PS/2和VGA控制显示控制器-FPGA and SOPC based on the use of VHDL language EDA s PS/2 and VGA display controller to control
Platform: | Size: 27648 | Author: 多幅撒 | Hits:

[VHDL-FPGA-Verilog] spi.tar

Description: SPI(serial port interface)的Verilog/VHDL源代碼，已模擬並驗證。-SPI (serial port interface) of the Verilog/VHDL source code, has been simulated and verified.
Platform: | Size: 116736 | Author: hcjian | Hits:

[Other] MEALY

Description: MEALY状态机的输出是现态和输入的函数.在SRAM控制器状态机中,写有效WE不仅和WRITE状态有关,还和总线命令WRITE_MASK有关.这样,输出WE信号按设计要求表示为现态WRITE和现态输入WRITE_MASK的函数.本程序基于VHDL,开发环境为MAXPLUS2-Mealy state machine output is now a function of state and input. In the SRAM controller state machine, the writing is not only effective WE and WRITE state, but also and bus-related WRITE_MASK command. In this way, WE output signal according to design requirements that the current state WRITE and is a function of state input WRITE_MASK. This procedure based on VHDL, development environment for MAXPLUS2
Platform: | Size: 29696 | Author: weixiaoyu | Hits:

[VHDL-FPGA-Verilog] my_zbt_controller

Description: ZBT内存控制器.支持OPB总线。VHDL源码-ZBT memory controller. Support the OPB bus. VHDL source
Platform: | Size: 1024 | Author: 吕奔 | Hits:

[VHDL-FPGA-Verilog] FPGA_VGA

Description: 基于FPGA的高分辨率VGA显示控制器的设计-FPGA-based high-resolution VGA display controller design
Platform: | Size: 291840 | Author: 火冰 | Hits:

[VHDL-FPGA-Verilog] ac97_verilog_sourcecode

Description: AC97芯片的verilog实现，有兴趣可以研究下。verilog是一种硬件开发语言，语法与c类似。与VHDL并列为IC开发两大编程语言-AC97 chip Verilog realize, who are interested can study. Verilog is a hardware development language, grammar and c similar. IC with VHDL as a programming language to develop two
Platform: | Size: 124928 | Author: 小步 | Hits:

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